1. Field of Invention
The present invention relates to a method and apparatus for accessing data from a dynamic access random memory (DRAM) of a computer. More particularly, the present invention relates to a method and apparatus capable of programmably delaying a clock of memory.
2. Description of Related Art
The main memory of a computer, such as a personal computer (PC), is used for storing data or information, which can be accessed by a central processing unit (CPU) of the PC. Namely, data can be stored within and read from the main memory and furthermore, program and data are executed or processed within the memory. Accompanying highly developed semiconductor technology, it is common for a modem PC to have tens or hundreds of megabytes (MB) of memory. In addition, the clock frequency of the memory rises up to 100 MHz or higher as the clock frequency of the CPU continuously increases.
As the clock frequency of the memory rises, the clock period of the memory is shortened. In addition, the clock sent from the north bridge (NB) of a PC is transmitted to the memory module, which is delayed when it passes through a transmission path on a print circuit board (PCB). When a memory module senses the command word asserted by the NB according to the rising edge of the clock, the memory module can't correctly read the command word because there is not enough setup time, which causes the PC to malfunction.
FIG. 1 is a schematic block diagram of a north bridge (NB) and DRAM module of a conventional PC. As shown in FIG. 1, the NB 10 comprises a phase locked loop (PLL) circuit 11 having two inputs for respectively receiving a command output clock signal (DCLK) and a feedback input clock signal (DCLKIN), which both have the same phase and frequency, and an output for outputting a bus output clock signal (DCLKO), which has the same frequency of DCLK but leads the DCLK by one phase. DCLKO is transmitted to the DRAM module 20 through a transmission path, and is fed back to PLL circuit 11 by the transmission path serving as signal DCLKIN. Because the transmission delay is substantially equal, the frequency and phase of DCLKIN detected at the input of PLL circuit is substantially equal to those of the memory input clock signal (CLK_DM) detected at the DRAM module 20.
FIG. 2A depicts a timing diagram of the north bridge when the north bridge accesses the DRAM module according to a conventional PC architecture. The command output clock signal DCLK is sent from the north bridge. Referring to FIGS. 1, 2A and 2B, at time T1, the north bridge 10 asserts a command word (CMD) to DRAM module 20, and the phase of the command word received at the DRAM module 20 is slightly delayed due to the transmission delay. As a result, there is not enough setup time while the DRAM module 20 tries to sense the command word CMD_DM at the rising edge of time T2 of memory input clock signal CLK_DM. This makes it impossible for the DRAM module 20 to send out correct data at time T3. Furthermore, the NB also lacks sufficient setup time to sense and read data from DRAM module 20 due to the transmission delay. Therefore, the NB 10 is unable to sense and read data from DRAM module 20. The situation is more serious when the memory is operated at a high speed or with heavy loading.